The electrical transport properties of nanocrystalline polycrystalline semiconductors often vary with grain size, but this correlation does not prove that size is the sole controlling factor. Grain size reduction is usually accompanied by increased grain boundary density, altering defect occupancy, depletion layer width, and cross-boundary barriers. This paper, based on a grain boundary barrier model, employs literature review and comparative analysis to synthesize experimental results from zero-dimensional quantum dot solids, one-dimensional polycrystalline silicon nanowires, and two-dimensional polycrystalline thin films, analyzing the different effects of geometric scale and grain boundary electrical activity on carrier transport. The results show that average grain size primarily affects the frequency of carrier encounters with the interface and the selectable conductive paths; the energy level, density, occupancy, and atomic structure of grain boundary states determine the degree of obstruction at a single interface and may simultaneously reduce carrier concentration and mobility. Grain boundary orientation, applied bias voltage, and illumination further alter local barriers and recombination behavior. Therefore, material evaluation should combine grain size statistics with local potential, atomic structure, and recombination kinetics, and employ grain boundary engineering techniques such as defect passivation, segregation control, or growth optimization based on the specific system.
Research Article
Open Access